The present invention relates generally to generation of clock signals for integrated circuits, and, more particularly to comparators and relaxation oscillators that use comparators.
Relaxation oscillator circuits are found in many electronic circuit applications and often are used for generating clock signals that control the timing of such electronic circuits. For example, relaxation oscillator circuits can be used in DC/DC converters, counters, shifters, microcontrollers, and modulation circuitry. Typically, the period of the clock signal provided by a relaxation oscillator circuit is determined primarily by the charging and discharging of two capacitors.
FIG. 1 shows a known relaxation oscillator circuit that has a reference voltage Vref, a first current source 101 that supplies charging current to a first capacitor 102, a first capacitor switch 103, a second current source 104 that supplies charging current to a second capacitor 105, a second capacitor switch 106, a first comparator 107, a second comparator 108 and a flip-flop 109 that provides an output clock signal. Third and fourth current sources 110 and 111 supply bias currents to the first and second comparators 107, 108 respectively. By operation of the first switch 103, the first capacitor 102 is charged during a first half-cycle of the output clock signal and discharged during a second half-cycle of the output clock signal. By operation of the second switch 106, the second capacitor 105 is charged during the second half-cycle of the output clock cycle and discharged during the first half-cycle of the output clock signal. The first comparator 107 is arranged to provide an output by continuously comparing the voltage across the first capacitor to the reference voltage Vref. The second comparator 108 is arranged to provide an output by continuously comparing the voltage across the second capacitor to the reference voltage Vref. The flip-flop 109 has Q and /Q outputs that generate the output clock signal CLK and an inverted output clock signal /CLK, which are provided to the comparators. The output clock signals CLK and /CLK operate the second and first switches 106, 103, respectively.
Power consumption of such a typical relaxation oscillator is relatively high because of the presence of the four current sources 101, 104, 110, and 111, which are required to be active for all charging and discharging phases of the capacitors 102 and 105. Moreover, in order to achieve good accuracy of the clock period, the response speed of the comparators should be sufficiently fast. This requires more power, which might not be acceptable in low power applications. It therefore would be advantageous to provide a relaxation oscillator that consumes less power.